Clock Delay

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Hi

I generate an internal master clock from a flip-flop and use it to clock the data to an external device. The FPGA logic also works on the same clock. The same clock is given out to the device. I can see from the report that the clock uses global routing. But the data given out by the external device to the FPGA (sampled using the master clock in the FPGA) fails to meet the set-up time of my FPGA. One reason being, the difference in clock delay between the launch clock and the latch clock. I was expecting the clock delays to be comparable, as it is the same clock which is given out and the clock has been globally routed (so that skew is minimal). I am attaching the timing diagram.

Am I missing something? It is a 50 MHz design and if the tco of external device is 16 ns and the data delay in the FPGA is around 5 ns, is there anyway the incoming data from the externnal device can meet the set-up of FPGA?

Thanks

Satish

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Hi,

in my point of view it could not work.

16ns + 5ns = 21 ns > 20ns ( clock period )

You have to reduce the tco of the external device or the input delay of the FPGA.

Kind regards

GPK

Hi

May be I need to get my basics right.

I have generated a trivial project just to understand the concepts. I am attaching the report/HDL/SDC/STA report/waveform.

Please let me know if the constraints make sense. The idea is, the whole system (FPGA plus external device) uses the same master clock generated in the FPGA. Lets say, for the external device, Tco = 18 wrt clock it recieves. Tsu = 10 and Th = 5.

Satish

1) Why are you creating a ripple-clock when you have a PLL? It would generally make more sense to have the PLL output a divide by 2 clock if that's what you want. (But for what you have, the generated clock assignment on it looks correct).

2) The generated clock on clk_out also looks correct except for the -divide_by 2. I don't believe that's necessary.

3) You're set_input_delay constraints are definitely wrong. The -clock option is used to specify the clock that drives the external register sending data to the FPGA. This is not clk_int. If an external clock drives the source device, then create a virtual clock like "create_clock -period 20.0 -name clk_ext" and use that. If the clock being sent off chip drives the upstream device, then use CLK_OUT.

4) For the timing.txt, re-run with -detail full_path. This will break out the clock path in more detail, which is what you want for I/O timing(for internal timing the clock paths are balanced, and full_path usually just clutters the report). What you should see is your Data Arrival Path is the clock coming in, through the PLL, through the toggle register and to the output port. Your Data Required should be your clock coming in, through the PLL, through the toggle register and out the clock port, minus your -max external delay. Look at that for a while and see if it makes sense.

I re-read that the whole system is run by the clock being sent off chip. As such, your inputs should be:

set_input_delay -max -clock CLK_OUT [get_ports inputnames*]

set_input_delay -min -clock CLK_OUT [get_ports inputnames*]

Your max and min values are the longest and shortest amount of time it takes from the clock leaving CLK_OUT to the data coming back to the input ports.

Hi Rysc

Your inputs on the sample project were very helpful. I can now understand how the set_input_delay command is to be given. Also my initial question on the reason for a large clock skew value was answered once I analysed the output of report_timing command in detail. May be I can get started now with the constraints for my actual design.

Satish