Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorClock Delay
Hi I generate an internal master clock from a flip-flop and use it to clock the data to an external device. The FPGA logic also works on the same clock. The same clock is given out to the device. ...
Altera_ForumHonored Contributor
Honored Contributorthe waveform view doesn't give enough information. Run report_timing with -file "timing.txt" and attach the .txt file(zip it first). Also show the .sdc constraints for the clock and I/O.
%20-%20Waveform.JPG){kind=link}