Clock Delay

1) Why are you creating a ripple-clock when you have a PLL? It would generally make more sense to have the PLL output a divide by 2 clock if that's what you want. (But for what you have, the generated clock assignment on it looks correct).

2) The generated clock on clk_out also looks correct except for the -divide_by 2. I don't believe that's necessary.

3) You're set_input_delay constraints are definitely wrong. The -clock option is used to specify the clock that drives the external register sending data to the FPGA. This is not clk_int. If an external clock drives the source device, then create a virtual clock like "create_clock -period 20.0 -name clk_ext" and use that. If the clock being sent off chip drives the upstream device, then use CLK_OUT.

4) For the timing.txt, re-run with -detail full_path. This will break out the clock path in more detail, which is what you want for I/O timing(for internal timing the clock paths are balanced, and full_path usually just clutters the report). What you should see is your Data Arrival Path is the clock coming in, through the PLL, through the toggle register and to the output port. Your Data Required should be your clock coming in, through the PLL, through the toggle register and out the clock port, minus your -max external delay. Look at that for a while and see if it makes sense.