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Altera_Forum
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16 years ago

Clock Delay

Hi I generate an internal master clock from a flip-flop and use it to clock the data to an external device. The FPGA logic also works on the same clock. The same clock is given out to the device. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Hi Rysc

Your inputs on the sample project were very helpful. I can now understand how the set_input_delay command is to be given. Also my initial question on the reason for a large clock skew value was answered once I analysed the output of report_timing command in detail. May be I can get started now with the constraints for my actual design.

Satish