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Altera_Forum
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16 years ago

Clock Delay

Hi I generate an internal master clock from a flip-flop and use it to clock the data to an external device. The FPGA logic also works on the same clock. The same clock is given out to the device. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Hi

May be I need to get my basics right.

I have generated a trivial project just to understand the concepts. I am attaching the report/HDL/SDC/STA report/waveform.

Please let me know if the constraints make sense. The idea is, the whole system (FPGA plus external device) uses the same master clock generated in the FPGA. Lets say, for the external device, Tco = 18 wrt clock it recieves. Tsu = 10 and Th = 5.

Satish