Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorClock Delay
Hi I generate an internal master clock from a flip-flop and use it to clock the data to an external device. The FPGA logic also works on the same clock. The same clock is given out to the device. ...
Altera_ForumHonored Contributor
Honored ContributorI re-read that the whole system is run by the clock being sent off chip. As such, your inputs should be:
set_input_delay -max -clock CLK_OUT [get_ports inputnames*] set_input_delay -min -clock CLK_OUT [get_ports inputnames*] Your max and min values are the longest and shortest amount of time it takes from the clock leaving CLK_OUT to the data coming back to the input ports.
%20-%20Waveform.JPG){kind=link}