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Altera_Forum
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16 years ago

Clock Delay

Hi I generate an internal master clock from a flip-flop and use it to clock the data to an external device. The FPGA logic also works on the same clock. The same clock is given out to the device. ...
Altera_Forum's avatar
Altera_Forum
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16 years ago

If you're constraining input ports to the FPGA, then something seems wrong, since the clock delay of the launch clock is generally 0ns, as you'd be using a virtual clock. Again, I can't determine what you're doing with the description and waveform. (If the 16ns Tco is fixed, there isn't anythign you can do externally, but a PLL can always help with internal timing if your device has one. I just think the constraints might be incorrect to begin with, in which case it doesn't make sense analyzing the results).