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Altera_Forum's avatar
Altera_Forum
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13 years ago

Can someone please help me get this to compile

I can get this to compile and ive been at it for two days I dont get it

Can someone please help me to find why it wont compile.

The issue seems to be from the top If condition that uses SIGNAL_in and A_reg;

If i comment that sensativity list out and that correspsonding of condition it will compile

Its just a counter that has signals that go in and out of it from other counters.

The SIGNAL_IN is a reg type from the counter stacked on top of it. The error is only in this .v file not the other counter.

Please help im pulling my hair out. 

module last_row_counter(A,OVERFLOW,CLK,RST, upcount,SIGNAL,SIGNAL_IN);
input wire CLK, RST, upcount;
input wire SIGNAL_IN;
output wire OVERFLOW;
output wire  A;
output wire SIGNAL;
reg OVERFLOW_reg;
reg  A_reg;
reg SIGNAL_reg;
 
assign SIGNAL=SIGNAL_reg;
assign A=A_reg;
assign OVERFLOW=OVERFLOW_reg;
 
always @ (posedge CLK or negedge RST)
begin
if (SIGNAL_IN==4'b0100 && A_reg== 4'b0010)
begin
A_reg<=4'b0000;
SIGNAL_reg<=4'b0000;
end
end
 
always @ (posedge CLK or negedge RST)
if (~RST) begin
 OVERFLOW_reg <= 1'b0;
 A_reg<= 4'b0000;
 SIGNAL_reg<=4'b0000;
end
else if ( upcount == 1 )
 
 begin
  
  
 if (A<9) begin
   A_reg <= A_reg + 1'b1;
 SIGNAL_reg<=SIGNAL_reg+1'b1;
   OVERFLOW_reg <= 1'b0;
  end
  else begin
   A_reg <= 4'b0000;
 SIGNAL_reg<=4'b0000;
  OVERFLOW_reg <= 1'b1;
  end
 
 end
 else
 begin
 
 if (A>2) begin  //This is my count down
  A_reg <= A_reg - 1'b1;
  OVERFLOW_reg <= 1'b0;
 end
 
 else begin
  A_reg <= 4'b1001;
  OVERFLOW_reg <= 1'b1;
  end
 end
 
 
endmodule

10 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    One problem is you are assigning values to A_reg and SIGNAL_reg in multiple always blocks.

    You can use signals in different always blocks but you should always assign them in only one always block.

    Hope this helps

    Pete
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    One problem is you are assigning values to A_reg and SIGNAL_reg in multiple always blocks.

    You can use signals in different always blocks but you should always assign them in only one always block.

    Hope this helps

    Pete

    --- Quote End ---

    Hi Thanks Pete

    I put inside of one always block and still no luck

    Here is what it looks like now 

    module last_row_counter(A,OVERFLOW,CLK,RST, upcount,SIGNAL,SIGNAL_IN);
input wire CLK, RST, upcount;
input wire SIGNAL_IN;
output wire OVERFLOW;
output wire  A;
output wire SIGNAL;
reg OVERFLOW_reg;
reg  A_reg;
reg SIGNAL_reg;
 
assign SIGNAL=SIGNAL_reg;
assign A=A_reg;
assign OVERFLOW=OVERFLOW_reg;
/*
always @ (posedge CLK or negedge RST)
begin
if (SIGNAL_IN==4'b0100 && A_reg== 4'b0010)
begin
A_reg<=4'b0000;
SIGNAL_reg<=4'b0000;
end
end
*/
always @ (posedge CLK or negedge RST)
if (SIGNAL_IN==4'b0100 && A_reg== 4'b0010)
begin
A_reg<=4'b0000;
SIGNAL_reg<=4'b0000;
end
if (~RST) 
begin
 OVERFLOW_reg <= 1'b0;
 A_reg<= 4'b0000;
 SIGNAL_reg<=4'b0000;
end
else if ( upcount == 1 )
 
 begin
  
  
 if (A<9) begin
   A_reg <= A_reg + 1'b1;
 SIGNAL_reg<=SIGNAL_reg+1'b1;
   OVERFLOW_reg <= 1'b0;
  end
  else begin
   A_reg <= 4'b0000;
 SIGNAL_reg<=4'b0000;
  OVERFLOW_reg <= 1'b1;
  end
 
 end
 else
 begin
 
 if (A>2) begin  //This is my count down
  A_reg <= A_reg - 1'b1;
  OVERFLOW_reg <= 1'b0;
 end
 
 else begin
  A_reg <= 4'b1001;
  OVERFLOW_reg <= 1'b1;
  end
 end
 
 
endmodule
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Here is a better version of with some added commments

    But as i said the problem only lies in one if clause with the SIGNAL_in && A-reg

    Hopefully someone can hep 

    module last_row_counter(A,OVERFLOW,CLK,RST, upcount,SIGNAL,SIGNAL_IN);
input wire CLK, RST, upcount;
input wire SIGNAL_IN;
output wire OVERFLOW;
output wire  A;
output wire SIGNAL;
reg OVERFLOW_reg;
reg  A_reg;
reg SIGNAL_reg;
 
assign SIGNAL=SIGNAL_reg;
assign A=A_reg;
assign OVERFLOW=OVERFLOW_reg;
/*
always @ (posedge CLK or negedge RST)
begin
if (SIGNAL_IN==4'b0100 && A_reg== 4'b0010)
begin
A_reg<=4'b0000;
SIGNAL_reg<=4'b0000;
end
end
*/
/*****************************************************************************************************************/
always @ (posedge CLK or negedge RST)
if (SIGNAL_IN==4'b0100 && A_reg== 4'b0010) /*This Is where my input and output signal control should lie.
               This is going To get a trigger from outside counter as a 
               refereance to where that counter is at.*/
 begin
  A_reg<=4'b0000;
  SIGNAL_reg<=4'b0000;
 end
/*****************************************************************************************************************/
else if (~RST) //This is the main reset control*/
 begin
  OVERFLOW_reg <= 1'b0;
  A_reg<= 4'b0000;
  SIGNAL_reg<=4'b0000;
 end
/*****************************************************************************************************************/
 else if ( upcount == 1'b1 ) //This is where the upcount starts
 begin
  if (A<2) 
 
 begin
  A_reg <= A_reg + 1'b1;
  SIGNAL_reg<=SIGNAL_reg+1'b1;
  OVERFLOW_reg <= 1'b0;
 end
/*****************************************************************************************************************/  
  //This is to limit the counter. When the counter reaches its limitation in this case 2 it will reset to zero
  else 
  
  begin
  A_reg <= 4'b0000;
  SIGNAL_reg<=4'b0000;
  OVERFLOW_reg <= 1'b1;
  end
 
 end
 /*****************************************************************************************************************/
 //This is the old downcount that has been turned off for now.
 
 /*else
 begin
 
 if (A>2) begin  //This is my count down
  A_reg <= A_reg - 1'b1;
  OVERFLOW_reg <= 1'b0;
 end
 
 else begin
  A_reg <= 4'b1001;
  OVERFLOW_reg <= 1'b1;
  end
 end
 */
 
endmodule
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Now you have issues with your begin/end statements:

    Here's a clue.

    Write your code like this:

    always @(posedge CLK or negedge RST)

    begin

    if (~RST)

    begin

    ...

    end

    else

    begin

    ...

    if (statement)

    ...

    end

    end
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    I thought that may be the issue but i the error is not with the begin and ends

    the compile error

    Error (10200): Verilog HDL Conditional Statement error at last_row_counter.v(37): cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct

    On this line

    if (SIGNAL_IN==4'b0100 && A_reg== 4'b0010)

    I went through all the begin and ends again i cannot not see any issue 

    module last_row_counter(A,OVERFLOW,CLK,RST, upcount,SIGNAL,SIGNAL_IN);
input wire CLK, RST, upcount;
input wire SIGNAL_IN;
output wire OVERFLOW;
output wire  A;
output wire SIGNAL;
reg OVERFLOW_reg;
reg  A_reg;
reg SIGNAL_reg;
 
assign SIGNAL=SIGNAL_reg;
assign A=A_reg;
assign OVERFLOW=OVERFLOW_reg;
/*
always @ (posedge CLK or negedge RST)
begin
if (SIGNAL_IN==4'b0100 && A_reg== 4'b0010)
begin
A_reg<=4'b0000;
SIGNAL_reg<=4'b0000;
end
end
*/
/*****************************************************************************************************************/
always @ (posedge CLK or negedge RST)
if (SIGNAL_IN==4'b0100 && A_reg== 4'b0010) /*This Is where my input and output signal control should lie.
               This is going To get a trigger from outside counter as a 
               refereance to where that counter is at.*/
 begin
  A_reg<=4'b0000;
  SIGNAL_reg<=4'b0000;
 end
/*****************************************************************************************************************/
else if (~RST) //This is the main reset control*/
 begin
  OVERFLOW_reg <= 1'b0;
  A_reg<= 4'b0000;
  SIGNAL_reg<=4'b0000;
 end
/*****************************************************************************************************************/
 else if ( upcount == 1'b1 ) //This is where the upcount starts
 begin
  if (A<2) 
 
 begin
  A_reg <= A_reg + 1'b1;
  SIGNAL_reg<=SIGNAL_reg+1'b1;
  OVERFLOW_reg <= 1'b0;
 end
/*****************************************************************************************************************/  
  //This is to limit the counter. When the counter reaches its limitation in this case 2 it will reset to zero
  else 
  
  begin
  A_reg <= 4'b0000;
  SIGNAL_reg<=4'b0000;
  OVERFLOW_reg <= 1'b1;
  end
 
 end
 /*****************************************************************************************************************/
 //This is the old downcount that has been turned off for now.
 
 /*else
 begin
 
 if (A>2) begin  //This is my count down
  A_reg <= A_reg - 1'b1;
  OVERFLOW_reg <= 1'b0;
 end
 
 else begin
  A_reg <= 4'b1001;
  OVERFLOW_reg <= 1'b1;
  end
 end
 */
 
endmodule
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    What's the exact error you are getting? On my previous post all the indenting got stripped away..

    The reset term should always be the first conditional especially since you are using an async reset.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Also just a side note i have tried to put begin right under the sensitivity list and then again at the very bottom like you suggest

    still no change
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    What's the exact error you are getting? On my previous post all the indenting got stripped away..

    The reset term should always be the first conditional especially since you are using an async reset.

    --- Quote End ---

    Everything works fine except for this line

    If i comment this line out it all works

    i need this line though.

    So if the reset needs to be first where do you suggest i put this line

    i just stuck it in there cuz the above someone receomended i needed to put it in the main always block 

    if (SIGNAL_IN==4'b0100 && A_reg== 4'b0010) /*This Is where my input and output signal control should lie.
               This is going To get a trigger from outside counter as a 
               refereance to where that counter is at.*/
 begin
  A_reg<=4'b0000;
  SIGNAL_reg<=4'b0000;
 end
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    I rearanged it with the reset back up top

    Still no luck

    Thanks for the continued help 

    module last_row_counter(A,OVERFLOW,CLK,RST, upcount,SIGNAL,SIGNAL_IN);
input wire CLK, RST, upcount;
input wire SIGNAL_IN;
output wire OVERFLOW;
output wire  A;
output wire SIGNAL;
reg OVERFLOW_reg;
reg  A_reg;
reg SIGNAL_reg;
 
 
assign SIGNAL=SIGNAL_reg;
assign A=A_reg;
assign OVERFLOW=OVERFLOW_reg;
 
/*
always @ (posedge CLK or negedge RST)
begin
if (SIGNAL_IN==4'b0100 && A_reg== 4'b0010)
begin
A_reg<=4'b0000;
SIGNAL_reg<=4'b0000;
end
end
 
*/
/*****************************************************************************************************************/
always @ (posedge CLK or negedge RST)
 
else if (~RST) //This is the main reset control*/
 begin
  OVERFLOW_reg <= 1'b0;
  A_reg<= 4'b0000;
  SIGNAL_reg<=4'b0000;
 end
/*****************************************************************************************************************/
if (SIGNAL_IN==4'b0100 && A_reg== 4'b0010) /*This Is where my input and output signal control should lie.
               This is going To get a trigger from outside counter as a 
               refereance to where that counter is at.*/
 begin
  A_reg<=4'b0000;
  SIGNAL_reg<=4'b0000;
 end
/*****************************************************************************************************************/
 else if ( upcount == 1'b1 ) //This is where the upcount starts
 begin
  if (A<2) 
 
 begin
  A_reg <= A_reg + 1'b1;
  SIGNAL_reg<=SIGNAL_reg+1'b1;
  OVERFLOW_reg <= 1'b0;
 end
/*****************************************************************************************************************/  
  //This is to limit the counter. When the counter reaches its limitation in this case 2 it will reset to zero
  else 
 
  begin
  A_reg <= 4'b0000;
  SIGNAL_reg<=4'b0000;
  OVERFLOW_reg <= 1'b1;
  end
 
 end
 /*****************************************************************************************************************/
 //This is the old downcount that has been turned off for now.
 
 /*else
 begin
 
 if (A>2) begin  //This is my count down
  A_reg <= A_reg - 1'b1;
  OVERFLOW_reg <= 1'b0;
 end
 
 else begin
  A_reg <= 4'b1001;
  OVERFLOW_reg <= 1'b1;
  end
 end
 */
 
endmodule
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Is the error message the same?

    Now you have a new error in that you are starting with an else if instead of just and if.

    Then the secondary if is not in the always block. (because no else condition on the reset)

    Things to try: Add more () to the code:

    double check begin end and if/else statements.

    try making it a sync reset block by removing the "or negedge RST" from the sensitivity list. (Although this shouldn't be the issue) with the async reset as the first statement.

    Try using bitwise and versus logical and "&" instead of "&&" in the if statement.

    use more () to insure no order of operation issue is the cause of your grief..

    IE

    if ((SIGNAL_IN==4'b0100) & (A_reg== 4'b0010))