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One problem is you are assigning values to A_reg and SIGNAL_reg in multiple always blocks.
You can use signals in different always blocks but you should always assign them in only one always block.
Hope this helps
Pete
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Hi Thanks Pete
I put inside of one always block and still no luck
Here is what it looks like now
module last_row_counter(A,OVERFLOW,CLK,RST, upcount,SIGNAL,SIGNAL_IN);
input wire CLK, RST, upcount;
input wire SIGNAL_IN;
output wire OVERFLOW;
output wire A;
output wire SIGNAL;
reg OVERFLOW_reg;
reg A_reg;
reg SIGNAL_reg;
assign SIGNAL=SIGNAL_reg;
assign A=A_reg;
assign OVERFLOW=OVERFLOW_reg;
/*
always @ (posedge CLK or negedge RST)
begin
if (SIGNAL_IN==4'b0100 && A_reg== 4'b0010)
begin
A_reg<=4'b0000;
SIGNAL_reg<=4'b0000;
end
end
*/
always @ (posedge CLK or negedge RST)
if (SIGNAL_IN==4'b0100 && A_reg== 4'b0010)
begin
A_reg<=4'b0000;
SIGNAL_reg<=4'b0000;
end
if (~RST)
begin
OVERFLOW_reg <= 1'b0;
A_reg<= 4'b0000;
SIGNAL_reg<=4'b0000;
end
else if ( upcount == 1 )
begin
if (A<9) begin
A_reg <= A_reg + 1'b1;
SIGNAL_reg<=SIGNAL_reg+1'b1;
OVERFLOW_reg <= 1'b0;
end
else begin
A_reg <= 4'b0000;
SIGNAL_reg<=4'b0000;
OVERFLOW_reg <= 1'b1;
end
end
else
begin
if (A>2) begin //This is my count down
A_reg <= A_reg - 1'b1;
OVERFLOW_reg <= 1'b0;
end
else begin
A_reg <= 4'b1001;
OVERFLOW_reg <= 1'b1;
end
end
endmodule
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