Can someone please help me get this to compile

I rearanged it with the reset back up top

module last_row_counter(A,OVERFLOW,CLK,RST, upcount,SIGNAL,SIGNAL_IN);
input wire CLK, RST, upcount;
input wire SIGNAL_IN;
output wire OVERFLOW;
output wire  A;
output wire SIGNAL;
reg OVERFLOW_reg;
reg  A_reg;
reg SIGNAL_reg;
 
 
assign SIGNAL=SIGNAL_reg;
assign A=A_reg;
assign OVERFLOW=OVERFLOW_reg;
 
/*
always @ (posedge CLK or negedge RST)
begin
if (SIGNAL_IN==4'b0100 && A_reg== 4'b0010)
begin
A_reg<=4'b0000;
SIGNAL_reg<=4'b0000;
end
end
 
*/
/*****************************************************************************************************************/
always @ (posedge CLK or negedge RST)
 
else if (~RST) //This is the main reset control*/
 begin
  OVERFLOW_reg <= 1'b0;
  A_reg<= 4'b0000;
  SIGNAL_reg<=4'b0000;
 end
/*****************************************************************************************************************/
if (SIGNAL_IN==4'b0100 && A_reg== 4'b0010) /*This Is where my input and output signal control should lie.
               This is going To get a trigger from outside counter as a 
               refereance to where that counter is at.*/
 begin
  A_reg<=4'b0000;
  SIGNAL_reg<=4'b0000;
 end
/*****************************************************************************************************************/
 else if ( upcount == 1'b1 ) //This is where the upcount starts
 begin
  if (A<2) 
 
 begin
  A_reg <= A_reg + 1'b1;
  SIGNAL_reg<=SIGNAL_reg+1'b1;
  OVERFLOW_reg <= 1'b0;
 end
/*****************************************************************************************************************/  
  //This is to limit the counter. When the counter reaches its limitation in this case 2 it will reset to zero
  else 
 
  begin
  A_reg <= 4'b0000;
  SIGNAL_reg<=4'b0000;
  OVERFLOW_reg <= 1'b1;
  end
 
 end
 /*****************************************************************************************************************/
 //This is the old downcount that has been turned off for now.
 
 /*else
 begin
 
 if (A>2) begin  //This is my count down
  A_reg <= A_reg - 1'b1;
  OVERFLOW_reg <= 1'b0;
 end
 
 else begin
  A_reg <= 4'b1001;
  OVERFLOW_reg <= 1'b1;
  end
 end
 */
 
endmodule