Altera_Forum
Honored Contributor
7 years agoCan I use this trick for CPLD MAX V small MBGA package
Hello,
I have designed a small board with a CPLD MAXV MBGA package(5M80ZM68I5) since I did not use all the pins and I did not want to use high tech board production which is expensive I used ordinary Vias(Already filled and capped) between pads and connect unused pins to intended pin. After mass production we see a problem in some boards, the only JTAG pin which is connected to unused pins is TDO(Attached Photo) in some board CPLD could not be flashed there TDO pin status is 0V whereas in other board which can be flashed TDO=3.3V what is the problem? do the unused pins affect on TDO? Do they have 0V state before flashing? what is the I/O state(0v or 3.3v) before flashing? Thanks in advance for your helps.