Forum Discussion
Honored ContributorBidirectional IOs in FPGA
Hi,
In my project, I have 2 bidirectional IO buses of 32-bit width. I need to connect both of them together for 2-way data transfer. I've tried two options in VHDL: bus1 <= bus2 This was mentioned in the help section of Quartus II. It mentions that we dont need to use any control signals for the direction of the IO. The tool will automatically handle this and effect the bidir transfer. I tried this option and it seems to work. The only prob is that data transfer one way is fast while the other way is slow with lots of delay ~20ns. This is not acceptable for me as I need the data at the appropriate time for latching it. I then changed some options in the tool (for max speed optimization) and now the above code snippet yields a warning stating that the transfer is only one way. Now I had to use the WE# signal to control the data flow: bus1 <= bus2 when we# = '0' else (others => 'Z'); (write transaction) bus2 <= bus1 when we# = '1' else (others => 'Z'); (read transaction) This synthesized without warnings or errors but the data transfer does not take place. Can anyone help me regarding this bidir data IO? I need this very urgently to finish my project. Thx4 Replies
Altera_ForumHello,
additionally, I think that it's physically impossible to achieve the function without a direction signal. I overlooked this point at first sight. Please notice, that physically nothing but a BIDIR primitive can be instantiated at each pin. It has an OE input, that must be controlled somehow. How can the logic determine data direction without a control signal? Regards, Frank- Altera_Forum
O.K. I see. Your designing something like a 245 bidirectional driver. Then I actually don't understand the reason for the delay. It must have a particulary reason from your design, e. g. available routing resources. Or the routing is influenced by additional logic connected to the bus signals. Can you verify in RTL respectively Technology Map Viewer that the compiler understands your logic right?
- Altera_Forum
well, the BUS1 and BUS2 are bidir IO pins. There is no other logic in between. I just need to connect them both to effect 2-way data transfer without much delay (~10ns). The WE# is also an input pin. Basically I'm trying to interface a DSP processor's SDRAM controller with a Micron SDRAM. The bidir IO are the data buses. While the other pins are the control pins. The problem lies with the data bus. I need to connect the data bus of the DSP to the SDRAM data via the FPGA. So the FPGA will have two sets of bidir IO pins - One for the DSP side and other for the SDRAM side.
- Altera_Forum
It's unclear from your question which signals are pins and which are internal. Can you please clarify the design structure?
