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Altera_Forum
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18 years ago

Bidirectional IOs in FPGA

Hi, In my project, I have 2 bidirectional IO buses of 32-bit width. I need to connect both of them together for 2-way data transfer. I've tried two options in VHDL: bus1 <= bus2 This...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

It's unclear from your question which signals are pins and which are internal. Can you please clarify the design structure?