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Altera_Forum
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18 years ago

Bidirectional IOs in FPGA

Hi, In my project, I have 2 bidirectional IO buses of 32-bit width. I need to connect both of them together for 2-way data transfer. I've tried two options in VHDL: bus1 <= bus2 This...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

O.K. I see. Your designing something like a 245 bidirectional driver. Then I actually don't understand the reason for the delay. It must have a particulary reason from your design, e. g. available routing resources. Or the routing is influenced by additional logic connected to the bus signals. Can you verify in RTL respectively Technology Map Viewer that the compiler understands your logic right?