Bidirectional IOs in FPGA

well, the BUS1 and BUS2 are bidir IO pins. There is no other logic in between. I just need to connect them both to effect 2-way data transfer without much delay (~10ns). The WE# is also an input pin. Basically I'm trying to interface a DSP processor's SDRAM controller with a Micron SDRAM. The bidir IO are the data buses. While the other pins are the control pins. The problem lies with the data bus. I need to connect the data bus of the DSP to the SDRAM data via the FPGA. So the FPGA will have two sets of bidir IO pins - One for the DSP side and other for the SDRAM side.