Bad Pins

Generally, deleting the db directory resets all previous compilation results.

Although there's always a possibility of revealing new Quartus bugs, your obervation sounds somewhat unlikely in my opinion. You didn't tell about your design implementation method, but you have the option to check the Place&Route result in the Technology Map Viewer.

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I am a rookie. I am working on my fourth MAX II design. I am using Quartus II Version 9 SP2.

The problem I am having is that several pins on EPM1270 do not work. For example. I have four test pins I use for debugging. If I connect the clock to all four of these pins (set up as outputs), the oscillator signal only comes out of one of the four test pins. (There are probably other pins that are not working, but I haven't found them yet.)

This seems like a Quartus problem to me. I would appreciate any advice. Especially, is there a file that I can delete that will ensure a complete re-build?

Thank you for any constructive suggestions.

John

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Hi John,

there a lot of possibilties why your design isn't working.

1. Your board or your MAX devcie is broken

Is it a new board or did you have run a design on it in the past ?

Can you assign your output to other pins ?

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2. Your design

Did you check that the clock is really connected to the outputs ?

Use the Quartus Tech View for checking.

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3. Quartus

Did you check your pin assignment ? Are the output assigned ??

One way to force Quartus to re-build the database is to delete the db folder.

Kind regards

GPK

Thanks to both of you for your suggestions. I will try them today.

I certainly don't expect that it would be a problem with Quartus, but it seems so strange. I worked with Quartus quite a bit about a year ago and never had any problems like this.

It is a new board. All the pins are assigned correctly.

Again thank you.

John

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Thanks to both of you for your suggestions. I will try them today.

I certainly don't expect that it would be a problem with Quartus, but it seems so strange. I worked with Quartus quite a bit about a year ago and never had any problems like this.

It is a new board. All the pins are assigned correctly.

Again thank you.

John

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Hi John,

is it possible that the board itself is the problem ?

An easy way to check what Quartus did with your design is to look into the RTL or Technology View.

Kind regards

GPK

Yes, it is certainly possible that there is something wrong with the board. But I have already verified about half of the functionality of this FPGA design. These test pins are only routed directly to Test-points on the board. (They are not connected to multiple places.)

Also I have had correct signals on these test pins earlier. Then several pins stopped working. Since I didn't know I could delete the db folder, I created a new design and re-drew the TOP block. I thought that had fixed the problem.

I am currently looking at the Technology Map Viewer, and all pins are shown correctly.

Thanks for your continued assistance.

John

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Yes, it is certainly possible that there is something wrong with the board. But I have already verified about half of the functionality of this FPGA design. These test pins are only routed directly to Test-points on the board. (They are not connected to multiple places.)

Also I have had correct signals on these test pins earlier. Then several pins stopped working. Since I didn't know I could delete the db folder, I created a new design and re-drew the TOP block. I thought that had fixed the problem.

I am currently looking at the Technology Map Viewer, and all pins are shown correctly.

Thanks for your continued assistance.

John

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Hi John,

are all your test pins located in one I/O Bank ?

Kind regards

GPK

Three of them are in Bank 2.

One is in Bank 3.

Why is this significant?

John

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Three of them are in Bank 2.

One is in Bank 3.

Why is this significant?

John

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Hi John,

If the one on Bank3 is running, I would assume that something is wrong with Bank2 of your Device.

Kind regards

GPK

Here is the situation:

The PC board has some analog circuitry that operates form a 5 VDC rail. The footprint for one of the components was incorrect, and it inadvertently fed current (from the 5V rail) into the 3.3V rail. I observed the 3.3V rail going up to 3.6V. I never saw it go higher than that. I assumed that this had not damaged the FPGA.

But today I replaced it and I think it is working properly now.

I certainly appreciate all the help. It is very comforting to know that this community is so accessible.

Thanks-

John

At this point I am humbled but mostly lost. I have cut out most of the logic and am now down to "glue" that amounts to about 45 LEs. I have four test pins that I reserved for debugging. Device is EPM1270.

If I build a new design that has no logic and just ties the clock input pin directly to all four test pins, it works. (The clock appears on all four test pins.) If I open the 45 LE project above and tie the four pins to the clock, I don't get the clock signal on any of the four outputs.

Here are the things that I have tried:

- I have tried this on two different computers.

- I have replaced the FPGA

- I have redrawn the logic

- I have deleted the DB folder

- I have re-installed Quartus II on my computer.

- Device does not get warm.

- I have checked all pin numbers

- VCC = 3.331

I can't come up with a strategy to solve this. I do get some warnings, nothing that looks significant.

I welcome any suggestions.

Regards- John