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Altera_Forum's avatar
Altera_Forum
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16 years ago

Bad Pins

I am a rookie. I am working on my fourth MAX II design. I am using Quartus II Version 9 SP2. The problem I am having is that several pins on EPM1270 do not work. For example. I have four test...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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Yes, it is certainly possible that there is something wrong with the board. But I have already verified about half of the functionality of this FPGA design. These test pins are only routed directly to Test-points on the board. (They are not connected to multiple places.)

Also I have had correct signals on these test pins earlier. Then several pins stopped working. Since I didn't know I could delete the db folder, I created a new design and re-drew the TOP block. I thought that had fixed the problem.

I am currently looking at the Technology Map Viewer, and all pins are shown correctly.

Thanks for your continued assistance.

John

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Hi John,

are all your test pins located in one I/O Bank ?

Kind regards

GPK