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Yes, it is certainly possible that there is something wrong with the board. But I have already verified about half of the functionality of this FPGA design. These test pins are only routed directly to Test-points on the board. (They are not connected to multiple places.)
Also I have had correct signals on these test pins earlier. Then several pins stopped working. Since I didn't know I could delete the db folder, I created a new design and re-drew the TOP block. I thought that had fixed the problem.
I am currently looking at the Technology Map Viewer, and all pins are shown correctly.
Thanks for your continued assistance.
John
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Hi John,
are all your test pins located in one I/O Bank ?
Kind regards
GPK
Honored Contributor
