Bad Pins

I would prefer not to post it for security reasons. Howver, if I don't make progress in the next day or two, I will sanitize it and put it up.

Regards- John

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I do not think that it is a Quartus problem.

I am having another board built to see if I can duplicate the problem on a second board.

It seems like it is related to my design, but I have not been able to prove that.

Thank you for continued support.

John

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Hi John,

can you post your project in the forum ?

Kind regards

GPK

I do not think that it is a Quartus problem.

I am having another board built to see if I can duplicate the problem on a second board.

It seems like it is related to my design, but I have not been able to prove that.

Thank you for continued support.

John

the first task is to identify the problem is of hardware or of software.

if you have another same type of pcb, you can try that pcb.

if the same problem existed on that pcb. it is the quartus software's problem.

if the problem is not same or problem disapear, the problem is pcb.

sometime the cpld's some pins will be damaged by static electricity,but other pins are good.

According to your posts, it's not clear, if you checked the connection of the said pin in the physical map. Most compiler (or user code related) errors would reveal there.

You can also post your test design as a Quartus archive (*.qar file).

If you assume, that's a Quartus bug, contact Altera support.

At this point I am humbled but mostly lost. I have cut out most of the logic and am now down to "glue" that amounts to about 45 LEs. I have four test pins that I reserved for debugging. Device is EPM1270.

If I build a new design that has no logic and just ties the clock input pin directly to all four test pins, it works. (The clock appears on all four test pins.) If I open the 45 LE project above and tie the four pins to the clock, I don't get the clock signal on any of the four outputs.

Here are the things that I have tried:

- I have tried this on two different computers.

- I have replaced the FPGA

- I have redrawn the logic

- I have deleted the DB folder

- I have re-installed Quartus II on my computer.

- Device does not get warm.

- I have checked all pin numbers

- VCC = 3.331

I can't come up with a strategy to solve this. I do get some warnings, nothing that looks significant.

I welcome any suggestions.

Regards- John

Here is the situation:

The PC board has some analog circuitry that operates form a 5 VDC rail. The footprint for one of the components was incorrect, and it inadvertently fed current (from the 5V rail) into the 3.3V rail. I observed the 3.3V rail going up to 3.6V. I never saw it go higher than that. I assumed that this had not damaged the FPGA.

But today I replaced it and I think it is working properly now.

I certainly appreciate all the help. It is very comforting to know that this community is so accessible.

Thanks-

John

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Three of them are in Bank 2.

One is in Bank 3.

Why is this significant?

John

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Hi John,

If the one on Bank3 is running, I would assume that something is wrong with Bank2 of your Device.

Kind regards

GPK

Three of them are in Bank 2.

One is in Bank 3.

Why is this significant?

John

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Yes, it is certainly possible that there is something wrong with the board. But I have already verified about half of the functionality of this FPGA design. These test pins are only routed directly to Test-points on the board. (They are not connected to multiple places.)

Also I have had correct signals on these test pins earlier. Then several pins stopped working. Since I didn't know I could delete the db folder, I created a new design and re-drew the TOP block. I thought that had fixed the problem.

I am currently looking at the Technology Map Viewer, and all pins are shown correctly.

Thanks for your continued assistance.

John

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Hi John,

are all your test pins located in one I/O Bank ?

Kind regards

GPK