Avalon-ST configuration with Agilex 3 fails

Hi,

I have implemented a kind of passive serial programming from a CPU using SPI and a shift register. The signals nSTATUS, nCONFIG, CONF_DONE, READY, and VALID are directly controlled by GPIOs. This works well except after a power cycle. After the system has powered up, the programming fails — CONF_DONE does not go high. All retries afterward succeed. I already went through the debugging guidelines but couldn’t find an issue. However, I have observed two things:

• The nSTATUS pin follows exactly the timing of the nCONFIG pin during the first attempt. Normally, nSTATUS is delayed and goes high later.
• The CPU must finish the complete programming cycle before retrying; otherwise, the FPGA remains stuck in this erroneous state.

I recorded some curves with a logic analyzer:

• full_timing.png:

• 1. Power cycle
  2. First configuration cycle fails
  3. Retry works
  4. Another cycle also works

• 2_start.png:
  • Beginning of cycle 2. Here, the nSTATUS pin follows exactly the timing of the nCONFIG pin.
• 2_3_restart.png:
  • End of cycle 2 and beginning of cycle 3.
• 4_start.png:
  • Another configuration cycle that works.

Any idea what could cause this problem?

Regards Samuel