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sleh's avatar
sleh
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1 month ago

Avalon-ST configuration with Agilex 3 fails

Hi, I have implemented a kind of passive serial programming from a CPU using SPI and a shift register. The signals nSTATUS, nCONFIG, CONF_DONE, READY, and VALID are directly controlled by GPIOs. Thi...
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Programmable Logic Device
sstrell's avatar
sstrell
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1 month ago

No screenshots were attached.

sleh's avatar
sleh
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1 month ago

Let's hope it works this time.

  • sleh's avatar
    sleh
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    1 month ago

    I checked the power-up sequence again and made sure that no input is driven when the power is turned on. I have no idea what could be causing the programming problem.

    Please help, Thanks

    • sleh's avatar
      sleh
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      1 month ago

      Hi Fakhrul,

      Thank you for the link. The Quartus programmer never reports an error when I program via JTAG.

      The problem I have is that programming via AVST fails the first time after power-up. The FPGA already shows strange behavior at the beginning when nConfig goes low, see attached image. The nSTATUS pin follows the timing of nCONFIG exactly, which is abnormal. There must be an explanation for this.