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New ContributorATX PLL error in FIT stage
L-Tile/H-Tile Transcever ATX PLL Intel Sttratix 10 FPGA IP used by PLL. The configured parameters are as shown in the figure below：
But during the FIT stage there will be an error as shown below：
My PHY is using L-Tile/H-Tile Transcever Native PHY Intel Stratix 10FPGA IP,set the VCCR_GXB and VCCT_GXB supply voltage for the transceiver to 1_0V, select GXT for transceiver channel type ,select Basic(Enhanced PCS) for Transceiver configuration rules, and set Data rate to 16000M. Use the default parameters for the rest of the settings.
