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lance9's avatar
lance9
Icon for New Contributor rankNew Contributor
2 years ago

ATX PLL error in FIT stage

L-Tile/H-Tile Transcever ATX PLL Intel Sttratix 10 FPGA IP used by PLL. The configured parameters are as shown in the figure below： But during the FIT stage there will be an error...
Configuration
Kshitij_Intel's avatar
Kshitij_Intel
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi,


As we do not receive any response from you on the previous answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Thank you,

Kshitij Goel