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lance9's avatar
lance9
Icon for New Contributor rankNew Contributor
1 year ago

ATX PLL error in FIT stage

L-Tile/H-Tile Transcever ATX PLL Intel Sttratix 10 FPGA IP used by PLL. The configured parameters are as shown in the figure below： But during the FIT stage there will be an error...
Configuration
Kshitij_Intel's avatar
Kshitij_Intel
Icon for Frequent Contributor rankFrequent Contributor
1 year ago

Hi,


Can you please try with the latest version and let me know your observations.


Also, try to implement standalone PHY IP with PLL and compile it.


And if issue still persists share your standalone project. I will look into it.


Thank you,

Kshitij Goel