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Altera_Forum's avatar
Altera_Forum
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13 years ago

Asynchronous Signal

Hi.

I have a problem that my FPGA design failing after several seconds. The code purposes isto measurement frequency from external signal generator (50kHz)*. I'm working with 50Mhz clock, LPM_Divide [0-27], Pipe Line [20], Fmax=90MHz.

On ModelSim, the code works perfectly, but on Altera Evaluation Board (Cyclone IV)- the code stuck!. Using Altera SignalTap, I sew that my state machine is missing states and even jump to undefended state (completely disregard from the "when others =>Idan_State_Machine<=Idle_State;" line at the end of the state machine??!!).

When I transfered the external input signal to another register and then used it in my code- the problem seems to be disappearing.

How this is even possible? I agree that I should expect for one clock latency due to diss synchronization between the external input signal to the FPGA main clock, but to sent the state machine to the undefined state?! To stuke the code?

*Using two falling edge (idan_input_signal is the external input):

This is the partial code that failed:

" elsif clk'event and clk='1' then

idan_input_signal_buf <= idan_input_signal;

case Idan_State_Machine is

when Idle_State =>

if (Idan_input_signal_buf = '1' and idan_input_signal = '0') then "

This is the partial code that didn't failed:

" elsif clk'event and clk='1' then

Idan_input_signal_buf <= Idan_Input_Signal;

idan_input_signal_buf_two <= idan_input_signal_buf;

case Idan_State_Machine is

when Idle_State =>

if (Idan_input_signal_buf_two = '1' and Idan_input_signal_buf = '0') then "

Thanks,

Idan

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    For conclusion: whether I run into timing problem or whether it's metastability problem, both of them should be dissipating if I'll use at least three synchronization register before I'll use the external data on my design. Am I right?

    --- Quote End ---

    Using at least 1 register will help; using two or more will make it more reliable so you should aim for at least two if possible.You should also set a false path exception, so Quartus will recognize the synchronization register chain.set_false_path -from [get_ports Idan_Input_Signal]
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    Using at least 1 register will help;

    --- Quote End ---

    It will work in the lab, but will at some time in the future fail, because a 'one stage synchroniser' may not not reliable enough, especially at high frequencies. So it is good practice to always use a synchroniser chain of at least two successive registers.

    Of course the lower the frequency of the sampling clock the more reliable a 'one stage' synchroniser gets up to the point where the clock period is sufficiently long enough to let every metastable condition settle in time for the next clock edge.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Two registers at least. Let me also answer the issue of probability that was raised by original post. The tool gives probability figures for asynchronous paths in terms of propagating through to the rest of design. One register will increase that dramatically.

    On the other hand an asynchronous signal hitting timing window will have 100% or so possibility of failure at that register. The original post was trying to compare the async signal with its registered version and that caused the problem quickly.