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Honored Contributor
Honored ContributorAsynchronous Signal
Hi. I have a problem that my FPGA design failing after several seconds. The code purposes isto measurement frequency from external signal generator (50kHz)*. I'm working with 50Mhz clock, LPM_Divi...
Altera_ForumHonored Contributor
Honored ContributorTwo registers at least. Let me also answer the issue of probability that was raised by original post. The tool gives probability figures for asynchronous paths in terms of propagating through to the rest of design. One register will increase that dramatically.
On the other hand an asynchronous signal hitting timing window will have 100% or so possibility of failure at that register. The original post was trying to compare the async signal with its registered version and that caused the problem quickly.
