Asynchronous Signal

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Using at least 1 register will help;

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It will work in the lab, but will at some time in the future fail, because a 'one stage synchroniser' may not not reliable enough, especially at high frequencies. So it is good practice to always use a synchroniser chain of at least two successive registers.

Of course the lower the frequency of the sampling clock the more reliable a 'one stage' synchroniser gets up to the point where the clock period is sufficiently long enough to let every metastable condition settle in time for the next clock edge.