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Altera_Forum
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13 years ago

Asynchronous Signal

Hi. I have a problem that my FPGA design failing after several seconds. The code purposes isto measurement frequency from external signal generator (50kHz)*. I'm working with 50Mhz clock, LPM_Divi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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For conclusion: whether I run into timing problem or whether it's metastability problem, both of them should be dissipating if I'll use at least three synchronization register before I'll use the external data on my design. Am I right?

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Using at least 1 register will help; using two or more will make it more reliable so you should aim for at least two if possible.You should also set a false path exception, so Quartus will recognize the synchronization register chain.set_false_path -from [get_ports Idan_Input_Signal]