Forum Discussion
New ContributorAsynchronous FIFO and discontinuous write clock
Hello,
The FPGA is a Cyclone 10LP (10CL016YU256I7G).
The FIFO is configured as separate write and read clocks, it is 32 words deep.
I have a design where the write clock is discontinuous. I have a difference between simulation and hardware behavior. In fact, all works great in simulation. However, it does not work as expected in hardware. I suppose that simulation model is not accurate with the real hardware.
What I observe, when I write the four words (full and empty signals are useless as I have another way of knowing how many words have been written), the first read is always 0 and the fourth read give me the penultimate word.
So, question is : can we use this asynchronous FIFO with a discontinuous write clock ?
Many thanks in advance for the help.
Steve
4 Replies
Steve-534B46Just some comment about SignalTap screenshot :
- empty signal works as excepted
- dout is wrong, after first read I get 0x0000 and 0x6C04 is excepted, after second read I get 0x6C04 and 0x6C05 is excepted
- rd signal works as excepted
- the value of din are 0x6C04 on first write, 0x6C05 on second write, 0x6C06 on third write and 0x6C07 on last write
- wr seems to work as excepted
The FIFO is 128 word deep.
There are no resync FF on asynchronous reset.
Thanks for reading
Steve
- Steve-534B46
And most importantly, where did the code 0x6C07 go?
ShengN_alteraSuper Contributor
Could you provide the simulation as well?
Possible attach both the simulation and signal tap waveform for clearer view?
- ShengN_altera
Any further update? Does the problem resolved?
Could you attach both simulation and stp waveform for comparison
