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Steve-534B46
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8 months ago

Asynchronous FIFO and discontinuous write clock

Hello, The FPGA is a Cyclone 10LP (10CL016YU256I7G). The FIFO is configured as separate write and read clocks, it is 32 words deep. I have a design where the write clock is discontinuous. I have a...
Core Logic
Programmable Logic Device
Steve-534B46's avatar
Steve-534B46
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8 months ago

Just some comment about SignalTap screenshot :

  • empty signal works as excepted
  • dout is wrong, after first read I get 0x0000 and 0x6C04 is excepted, after second read I get 0x6C04 and 0x6C05 is excepted
  • rd signal works as excepted
  • the value of din are 0x6C04 on first write, 0x6C05 on second write, 0x6C06 on third write and 0x6C07 on last write
  • wr seems to work as excepted

The FIFO is 128 word deep.

There are no resync FF on asynchronous reset.

Thanks for reading

Steve