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ALTERA-INSUPPORT22
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2 years ago

Assistance Needed: Trouble Running Bare-Metal Code on second core Cyclone 5 HPS


I am working on intel cyclone 5 hps I have two cores in a processor Core 0 core 1, I want two code to run on two different cores core 0 and core 1 in bare metal .


When I run in jtag mode it works, for jtag i first debug using core 0 where i take core 1 out of reset it, than debug core 1 usign jtag it work


BUT, When i want to run both core usign qspi it only run core 0 not core 1


Here is the step i followed

Firsly, loading preloader
quartus_hps -c 1 -o P preloader-mkpimage.bin

I make an image from bin file of core 0 and place it to qspi

mkimage -A arm -O u-boot -T standalone -C none -a 0x00060000 -e 0 -n "baremetal image" -d core0.bin core0.img

quartus_hps -c 1 -o P -a 0x00060000 core0.img

I make an image from bin file of core 1 and place it to qspi
mkimage -A arm -O u-boot -T standalone -C none -a 0x00100000 -e 0 -n "baremetal image" -d core1.bin core1.img
quartus_hps -c 1 -o P -a 0x00100000 core1.bin


When i restart board only that code work which is in core 0, core 1 code not executing

I am setting cpu1startaddress 100000 apart from that in the code of core 0 also i am using alt_qspi function to to place bin file data in ddr,

I want to run in smp mode so I also set required aux_control_register smp and fw bit as stated in tech ref manual


alt_qspi_read((uint32_t *)BL_START/*ddr3 address*/, 0x100000/*qspi address*/, 0x40000);


In linker/scat file core 0 entry point is 0x60000 and

linker/scat file core 1 entry point is 0x100000

Board Debug
Configuration
Fpga Devkit

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