Assistance Needed: Trouble Running Bare-Metal Code on second core Cyclone 5 HPS

Hi

This is what I could gathered.

You would need to bring the core1 up in your main application in core0.

As stated in this document

https://developer.arm.com/documentation/ddi0407/i/clocks--resets--and-power-management/power-management/multiprocessor-bring-up?lang=en

From the Register map you would need to write to the SCU

https://www.intel.com/content/www/us/en/programmable/hps/cyclone-v/hps.html#sfo1410068407646.html

First set the bits of address 0xFFFEC00C to 0xFFFEC010 with 0. This invalidates all the SCU for all cores.

Then you could set the bits of address 0xFFFEC005 with 0. This enable the SMP mode for all cores.

Could you also share me your current project files that you have done so far?

So that I could test the flow out on my end too.

Regards

Jingyang, Teh