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New ContributorArria10 FPGA LVDS input assignment
Hi，
I want to assign a lvds input pin in the Arria10 FPGA without LVDS RX IP, the bank VCCIO is 1.8V.
I have used the quartus Assignment Editor to do the configuration as follows.
Both PIN_A32 and PIN_A26 are the P pins of a differential IO pair.
But the compilation result of the lvds_ser_i is always LVCOMS 1.8V
So, is there something wrong for my configuration, and I wonder to ask how to assign a input pin to the LVDS standard without LVDS IP core. Thank you!
3 Replies
Luca_LiuHi,
The configration in the first figure is correct.
I have started up a new empty project, which only have two input pins and two output pins.
The configuration could work well, so I think there is something wrong in my original environment.
Brs.
FakhrulA_alteraRegular Contributor
I’m glad your question has been addressed. I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get support from Altera experts. Otherwise, community users can continue to help you in this thread. Thank you.
- FakhrulA_altera
I’m glad your question has been addressed. I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get support from Altera experts. Otherwise, community users can continue to help you in this thread. Thank you.
