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Luca_Liu's avatar
Luca_Liu
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1 month ago

Arria10 FPGA LVDS input assignment

Hi， I want to assign a lvds input pin in the Arria10 FPGA without LVDS RX IP, the bank VCCIO is 1.8V. I have used the quartus Assignment Editor to do the configuration as follows.  Both PIN_A32 an...
Configuration
Luca_Liu's avatar
Luca_Liu
Icon for New Contributor rankNew Contributor
1 month ago

Hi,

The configration in the first figure is correct.

 I have started up a new empty project, which only have two input pins and two output pins.

The configuration could work well, so I think there is something wrong in my original environment. 

Brs.

FakhrulA_altera's avatar
FakhrulA_altera
Icon for Regular Contributor rankRegular Contributor
1 month ago

I’m glad your question has been addressed. I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get support from Altera experts. Otherwise, community users can continue to help you in this thread. Thank you.

  • FakhrulA_altera's avatar
    FakhrulA_altera
    Icon for Regular Contributor rankRegular Contributor
    1 month ago

    I’m glad your question has been addressed. I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get support from Altera experts. Otherwise, community users can continue to help you in this thread. Thank you.