Are warnings encountered during compilation flow safe to ignore?

Question

I was trying a rocketboard design in quartus and I am encountering a lot of warnings(during Analysis,Fitter and Timing estimate) in the compilation process. Are the warnings safe to ignore and still expect my design to work without any issue on board(FPGA).

My aim is actually to use this example of rocketboard as a reference and achieve my design by making minor modifications. So can I expect my design to work without any performance violation on board with these warnings still present or should I resolve them in all cases?

altera_forum · Answer

It depends what the warnings are (and unfortunately, Altera IP can throw up 1000s of warnings).

Warnings range from unused code in design files to whole blocks of logic being removed from the design because you forgot to connect something. The first set of warnings would be safe to ignore and design will work, but with the second one the design definitely wont work (as logic will be missing).

Because Quartus can swamp you with warnings, my usual flow would be to assume Ive got it correct and then browse the warnings for tell-tale problems (logic removed etc) when it doesnt work.

If the HDL code is all yours, then its easy to clear up the warnings. But usually you have altera IP in there, so clearing them just wont be possible.

altera_forum · Answer

Also - some designers deliberately write code that allows the synthesisor to throw logic away. This may be for easy of code readability, re-use or configurability. Either way, clearing up warnings in FPGA designs is practically impossible

altera_forum · Answer

Thanks Tricky for the immediate response.

Most of the design part will be Altera IP and only I have added a top file to the design and used custom logic in there. No warnings are present for the file which I have created. All the warnings which I encounter are with PCIe hard IP. Any idea on how these can be minimised? They are leading to unconstrained paths in timing due to the warnings.

altera_forum · Answer

the warnings wont lead to unconstrained paths - this will be because stuff is missing in your SDC files.

altera_forum · Answer

Let me cross check on that part once again as I used the sdc files of rocketboard with altered names.

My warning reads something like this:

Warning (332060): Node:top|inst|altera_pcie_a10_hip_161_xfln4sipcie_a10_hip_1|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|altera_xcvr_native_a10_161_vhre4dyhy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm2:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm2:inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_txclk_reg.reg was determined to be a clock but was found without an associated clock assignment.

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Are warnings encountered during compilation flow safe to ignore?

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