Are warnings encountered during compilation flow safe to ignore?

It depends what the warnings are (and unfortunately, Altera IP can throw up 1000s of warnings).

Warnings range from unused code in design files to whole blocks of logic being removed from the design because you forgot to connect something. The first set of warnings would be safe to ignore and design will work, but with the second one the design definitely wont work (as logic will be missing).

Because Quartus can swamp you with warnings, my usual flow would be to assume Ive got it correct and then browse the warnings for tell-tale problems (logic removed etc) when it doesnt work.

If the HDL code is all yours, then its easy to clear up the warnings. But usually you have altera IP in there, so clearing them just wont be possible.