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Altera_Forum
Honored Contributor
Honored ContributorAre warnings encountered during compilation flow safe to ignore?
I was trying a rocketboard design in quartus and I am encountering a lot of warnings(during Analysis,Fitter and Timing estimate) in the compilation process. Are the warnings safe to ignore and still ...
Altera_ForumHonored Contributor
Honored ContributorYes, thats a warning from timing analysis, not from the design itself.
If you altered the names of the paths in the sdc file - is it possible you got the paths wrong, or you have forgotten some command like derive_pll_clocks from the sdc file?
