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Altera_Forum
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9 years ago

Are warnings encountered during compilation flow safe to ignore?

I was trying a rocketboard design in quartus and I am encountering a lot of warnings(during Analysis,Fitter and Timing estimate) in the compilation process. Are the warnings safe to ignore and still ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Also - some designers deliberately write code that allows the synthesisor to throw logic away. This may be for easy of code readability, re-use or configurability. Either way, clearing up warnings in FPGA designs is practically impossible