Are warnings encountered during compilation flow safe to ignore?

Now I don't have issues with the altered path as I have taken the path from the STA report generated. I have used derive_pll_clocks but even then the timing issue is present. Now when I was going through other warnings, I got the below one. Can this lead to my previously posted warning?

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Warning (18708): ATX/FPLL < top|inst|altera_pcie_a10_hip_161_ivbokga : pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|lcpll_g3xn:g_pll.g_pll_g3n.lcpll_g3xn|altera_xcvr_atx_pll_a10_161_ekr4poq:lcpll_g3xn|a10_xcvr_atx_pll:a10_xcvr_atx_pll_inst|twentynm_atx_pll_inst > is not placed in the same bank as the reference clock.

To which pin is this warning referring to? I am unable to locate it from the messages. i have multiple instances of PCIe and i get same warning for each. So is this something to do with pin assignment of PCIE refclk?

*Sorry couldn't disable the smileys appearing so had to give spaces in between