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Altera_Forum
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8 years ago

Are warnings encountered during compilation flow safe to ignore?

I was trying a rocketboard design in quartus and I am encountering a lot of warnings(during Analysis,Fitter and Timing estimate) in the compilation process. Are the warnings safe to ignore and still ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Thanks Tricky for the immediate response.

Most of the design part will be Altera IP and only I have added a top file to the design and used custom logic in there. No warnings are present for the file which I have created. All the warnings which I encounter are with PCIe hard IP. Any idea on how these can be minimised? They are leading to unconstrained paths in timing due to the warnings.