Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Are warnings encountered during compilation flow safe to ignore?

I was trying a rocketboard design in quartus and I am encountering a lot of warnings(during Analysis,Fitter and Timing estimate) in the compilation process. Are the warnings safe to ignore and still ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

I have got a better view on the issue now. The warning which I have posted above (both the warnings) occurs only if my PCIe is gen3x4 RP. When it is gen2x4 RP(rocketboard design) none of these are present.

RP - root port

Is there something additional to be constrained when i change my pcie from gen2 to gen3?