Appropriate ADC for educational project?

Dear Amilcar,

This LPF that you sent me on the verilog code.

What values has implement on the LPF? and which is the Cut-off Frequency?

If I want change the Cut-off frequency i will change these signals?

logic signed [3*utils::MinBits(DECIMATION-1)+1:0] DELTA1 = 1'd0;

logic signed [3*utils::MinBits(DECIMATION-1)+1:0] CN1, CN2 = 1'd0;

logic signed [3*utils::MinBits(DECIMATION-1)+1:0] CN3, CN4;

logic signed [3*utils::MinBits(DECIMATION-1)+1:0] DN0, DN1, DN3, DN5 = 1'd0;

thank you again.

The LPF is a function of the decimation.

Please read this: http://www.ti.com/lit/gpn/ads1202 it will explain all the formulas.

Amilcar, could you please send us the initial sinc3+decimation code in VHDL, which you had sent us translated to Verilog?

Also, regarding the interface of ads1202 onto the fpga, the standard in mode 3 using an external clock is a unidirectional SPI bus using only MOSI function and assuming the ADC to be the master, isn't it? Any example code in VHDL?

Thanks in advance!

Isn't the code in TI AN SBAA094?

It's not actually SPI, simply a clock and a serial data stream:

process(MCLK, RESn)
begin
  if RESn = '0' then
    DELTA1 <= (others => '0');
  elsif MCLK'event and MCLK = '1' then
    if MOUT = '1' then
      DELTA1 <= DELTA1 + 1;
    end if;
  end if;
end process;

FvM you are right, but SBAA094 is regarding to ADS1202 in modes 0-2, operating with the internal clock. We are thinking of using the ads1202 in mode 3 operation with an external clock of 20MHz.

Ads1202 datasheet, regarding mode 3, refers that data will be sent every 2nd cycle of clock.

Also, the application shown in SBAA094 is supposed to be connected to some further DSP, which in our case is not the fact. We intend to keep data on the fpga, after filter and decimation process, so CN5 will actually NOT be an output.

As far as we can understand, RESN (reset?) is driven by the DSP, so we should control this somehow else, shouldn't we?

Regarding to SBAA094 on page 15, there is some kind of clock divider implemented. I got attached a datasheet we found, could you please have a look?! It is referring to ads1202 operating speciffically in mode 3.

I also attach you the Verilog code Amilcar had sent to me, as it seems to be all done in there!

Thank you very much for your interest!

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the application shown in SBAA094 is supposed to be connected to some further DSP, which in our case is not the fact.

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I don't see a relevant difference for the ADC data interface and decimator operation.

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As far as we can understand, RESN (reset?) is driven by the DSP

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Most FPGA designs have a reset signal, either an external input or derived from internal POR. For the ADC interface and decimator, it's not absolutely required, I think.

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Regarding to SBAA094 on page 15, there is some kind of clock divider implemented.

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As the text explains, it's their way to setup the decimation ratio. With mode 3, a clock divider is needed to supply the ADS1202 clock, which is something different. Mode 3 interface has an additional difficulty in so far, as it must recover the correct clock edge from the data. Unless you want to use a variable clock rate for the ADS1202 (I don't know exactly, what shall be the purpose at all), you don't have a benefit from mode 3 in my opinion. The datasheet shows somewhat different performance data for mode 3, but there's no clear advantage or disadvantage for this operation mode.

P.S.: The main advantage of mode 3 is an crystal accurate sampling frequency. It may be needed in some applications.

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Unless you want to use a variable clock rate for the ADS1202 (I don't know exactly, what shall be the purpose at all), you don't have a benefit from mode 3 in my opinion.

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How else are the adc and fpga supposed to be synchronized, when not wanting to use the internal clock of the adc for whole the system?

We need 20MHz for 10BASE -T Ethernet transmission after processing data to be properly encapsulated into packets.

process(RESN, CNR)
begin
if RESN = '0' then
DN0 <= (others => '0');
DN1 <= (others => '0');
DN3 <= (others => '0');
DN5 <= (others => '0');
elsif CNR'event and CNR = '1' then
DN0 <= CN2;
DN1 <= DN0;
DN3 <= CN3;
DN5 <= CN4;
end if;
end process;

What about this CNR, how is that produced?

Did you have a look at Amilcars' code?

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How else are the adc and fpga supposed to be synchronized, when not wanting to use the internal clock of the adc for whole the system?

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Also a free running ADC output (clock and data) can be synchronized to the system clock.

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What about this CNR, how is that produced?

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It's the output of the said "page 15" clock divider. It's bad coding style to use it in an edge sensitive process. I fear, the TI application note must be used rather carefully. Amilcar has implemented the clock divider in his code, too.

Ok so we will use it in mode 1 with the 10MHz standard, and get 50% of general system delay having the rest of the implementation running at 20MHz. You are right, that should actually not be such a problem. We were stuck on the idea of using one unified system clock. Anyway..

A decimation rate of 256 will give us about 40kHz of data rate and a 24-bit resolution, superb quality for our purpose of application. Will the tradeoff of filter-response due to that affect the rest of our implementation?

So do you think that we should use Amilcars' code?

Because in SBAA094 the clock divider is not introduced at all.

Using Amilcars' code, clock divider & decimation ratio definition is included, not as in SBAA094 proposal of analog switch input of decimation rate.

It's actually quite smart, having that implemented in this way.

What's your opinion?