Appropriate ADC for educational project?

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How else are the adc and fpga supposed to be synchronized, when not wanting to use the internal clock of the adc for whole the system?

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Also a free running ADC output (clock and data) can be synchronized to the system clock.

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What about this CNR, how is that produced?

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It's the output of the said "page 15" clock divider. It's bad coding style to use it in an edge sensitive process. I fear, the TI application note must be used rather carefully. Amilcar has implemented the clock divider in his code, too.