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the application shown in SBAA094 is supposed to be connected to some further DSP, which in our case is not the fact.
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I don't see a relevant difference for the ADC data interface and decimator operation.
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As far as we can understand, RESN (reset?) is driven by the DSP
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Most FPGA designs have a reset signal, either an external input or derived from internal POR. For the ADC interface and decimator, it's not absolutely required, I think.
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Regarding to SBAA094 on page 15, there is some kind of clock divider implemented.
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As the text explains, it's their way to setup the decimation ratio. With mode 3, a clock divider is needed to supply the ADS1202 clock, which is something different. Mode 3 interface has an additional difficulty in so far, as it must recover the correct clock edge from the data. Unless you want to use a variable clock rate for the ADS1202 (I don't know exactly, what shall be the purpose at all), you don't have a benefit from mode 3 in my opinion. The datasheet shows somewhat different performance data for mode 3, but there's no clear advantage or disadvantage for this operation mode.
P.S.: The main advantage of mode 3 is an crystal accurate sampling frequency. It may be needed in some applications.
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