Appropriate ADC for educational project?

FvM you are right, but SBAA094 is regarding to ADS1202 in modes 0-2, operating with the internal clock. We are thinking of using the ads1202 in mode 3 operation with an external clock of 20MHz.

Ads1202 datasheet, regarding mode 3, refers that data will be sent every 2nd cycle of clock.

Also, the application shown in SBAA094 is supposed to be connected to some further DSP, which in our case is not the fact. We intend to keep data on the fpga, after filter and decimation process, so CN5 will actually NOT be an output.

As far as we can understand, RESN (reset?) is driven by the DSP, so we should control this somehow else, shouldn't we?

Regarding to SBAA094 on page 15, there is some kind of clock divider implemented. I got attached a datasheet we found, could you please have a look?! It is referring to ads1202 operating speciffically in mode 3.

I also attach you the Verilog code Amilcar had sent to me, as it seems to be all done in there!

Thank you very much for your interest!