Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Appropriate ADC for educational project?

Hello folks!

I'm a student of 'Network Systems and Data Communications' department in Greece and am doing my final project/dissertation right now in Leiria, Portugal at Electrical Engineering department.

Because the subject is kind of complex, I'm going to introduce to you only the part on which I'd like to set my specific question.

I want to implement a small device/circuit which will be inputted some analog voice commands from a normal electret mic. Till now I'm not clear about what pre-amp/op-amp I should use, but I believe I'll figure this out.

The implemented circuit will be interfaced onto a Pluto-II (Cyclone-I) FPGA board, probably SPI/i2c will fit the best. I've read a lot about ADC's appropriate for voice/audio systems, and I suggest that an Σ-Δ (sigma-delta) ADC will be good for me, in combination of a simple low-pass anti-aliasing filter consisting of a resistor and a capacitor in parallel before the ADC.

Actually, regarding the Σ-Δ ADC I still have no clear image if it is a linear or logarithmic ADC, cause as far as I know, it should be a logarithmic one for audio sampling, isn't it?

Considering a specific topic of your forum and obvious knowledge you people got, I thought that maybe you could suggest to me any appropriate market ADC for my purpose.

Thank you!

Sincerely,

David

32 Replies

Show More
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    If I understand right, Amilcar's code is based on a clocking scheme similar to mode 3. He should comment on it himself. In the description, it's said the ADC clock is derived from system clock, which would imply mode 3 and additional external logic. This understanding is also suggested by the fact, that the ADC clock (i_ds_clk_out) isn't treated as an unrelated clock, which would need another synchronization stage.

    But the code is dedicated to ADS1204 which has a built-in clock divider and in contrast ADS1202 sends a clock at data rate rather than twice the data rate. So for either mode you choose some design modifications are necessary.

    At this point, I tend to follow your previous consideration to prefer mode 3.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Dear amilcar,

    Can you specify in which mode should will we use the ADS_1202 so that we can use the source code you gave us?

    But i can say that your code is very smart because you include decimation and the clock devider for the (i_ds_clk_out).

    Please explain 2-3 things about the modes you use, and the clocks' frequencies!!

    Thank you