Appropriate ADC for educational project?

If I understand right, Amilcar's code is based on a clocking scheme similar to mode 3. He should comment on it himself. In the description, it's said the ADC clock is derived from system clock, which would imply mode 3 and additional external logic. This understanding is also suggested by the fact, that the ADC clock (i_ds_clk_out) isn't treated as an unrelated clock, which would need another synchronization stage.

But the code is dedicated to ADS1204 which has a built-in clock divider and in contrast ADS1202 sends a clock at data rate rather than twice the data rate. So for either mode you choose some design modifications are necessary.

At this point, I tend to follow your previous consideration to prefer mode 3.