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Altera_Forum
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16 years ago

Appropriate ADC for educational project?

Hello folks! I'm a student of 'Network Systems and Data Communications' department in Greece and am doing my final project/dissertation right now in Leiria, Portugal at Electrical Engineering d...
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Altera_Forum
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15 years ago

Ok so we will use it in mode 1 with the 10MHz standard, and get 50% of general system delay having the rest of the implementation running at 20MHz. You are right, that should actually not be such a problem. We were stuck on the idea of using one unified system clock. Anyway..

A decimation rate of 256 will give us about 40kHz of data rate and a 24-bit resolution, superb quality for our purpose of application. Will the tradeoff of filter-response due to that affect the rest of our implementation?

So do you think that we should use Amilcars' code?

Because in SBAA094 the clock divider is not introduced at all.

Using Amilcars' code, clock divider & decimation ratio definition is included, not as in SBAA094 proposal of analog switch input of decimation rate.

It's actually quite smart, having that implemented in this way.

What's your opinion?