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Unless you want to use a variable clock rate for the ADS1202 (I don't know exactly, what shall be the purpose at all), you don't have a benefit from mode 3 in my opinion.
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How else are the adc and fpga supposed to be synchronized, when not wanting to use the internal clock of the adc for whole the system?
We need 20MHz for 10BASE -T Ethernet transmission after processing data to be properly encapsulated into packets.
process(RESN, CNR)
begin
if RESN = '0' then
DN0 <= (others => '0');
DN1 <= (others => '0');
DN3 <= (others => '0');
DN5 <= (others => '0');
elsif CNR'event and CNR = '1' then
DN0 <= CN2;
DN1 <= DN0;
DN3 <= CN3;
DN5 <= CN4;
end if;
end process;
What about this CNR, how is that produced?
Did you have a look at Amilcars' code?
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