Appropriate ADC for educational project?

Amilcar, could you please send us the initial sinc3+decimation code in VHDL, which you had sent us translated to Verilog?

Also, regarding the interface of ads1202 onto the fpga, the standard in mode 3 using an external clock is a unidirectional SPI bus using only MOSI function and assuming the ADC to be the master, isn't it? Any example code in VHDL?

Thanks in advance!