ALTPLL For Multiple Input Frequencies

Hi @BigSid

There is clock switchover features in certain variant of devices but I believe still not sufficient to accommodate 65k different frequencies. Looks like reconfiguration is the way to go. May we know how you want to use these different clocks in your design?

thanks.

Eng Wei

Hello.

The design has 65,536 discrete input frequency values, ranging from 50kHz to 450kHz. The ALTPLL minimum input frequency is 5MHz, correct? If so, do any frequency multiplication megafunctions exist (I'm using a Cyclone III device but will upgrade if necessary) to allow for increasing this range so that it's above the 5MHz minimum before being input into an ALTPLL? If not, I'll add a clock multiplier outside the FPGA first and divide by an equal scale in the ALTPLL to restore the 50kHz to 450kHz range.

The goal is to use ALTPLLs (with reconfiguration) to generate six output clocks at specified phases with respect to the input clock. I've found an example in the literature (see Figure 7 attachment) that shows three ROMs being created to allow for selection from one of three different input frequencies. I have 65,536 different input frequencies. Is there a way to achieve this without creating 65,536 ROMs?

Thanks.